Everything goes here, everything that is related to the ASIC world. No flames and no advertisements from agencies please. We discuss everything that appeals to the professionals in the ASIC field. Keywords: ASIC design, Verification,Vera, Specman, Synthesis, Verilog, VHDL, Synopsys, FPGA, CPLD, Altera, Xilinx, Atmel, DSP, EDA tools, job environment, place and route, PLI, Perl, Tcl, Nawk, Skill, Unix, C++, digital logic design, SOC, system design, CPU architecture, network, video, audio, DSP, chip architect. http://tech.groups.yahoo.com/group/ASICDESIGN/#ans Tags: asic, yahoo
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