Anton Gerasimov

ARM Synchronization Primitives

Thu, 12 Nov 2009 12:46:37 GMT

1.2.3. Memory barriers

To ensure a consistent memory view, it is architecturally defined that software must perform a Data Memory Barrier (DMB) operation:

between acquiring a resource, for example through locking a mutex or decrementing a semaphore, and making any access to that resource
before making a resource available, for example through unlocking a mutex or incrementing a semaphore

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGIEIE.html

Memory Management on the StrongARM

Wed, 11 Nov 2009 11:35:51 GMT

Memory Management on the StrongARM SA-110: An Application Note

http://www.renan.org/ARM/doc/MMSAAN.pdf

Cell Broadband Engine processor DMA engines

Mon, 09 Nov 2009 18:29:12 GMT

http://www.ibm.com/developerworks/power/library/pa-celldmas/
PPC/ SPE/ MFC Interface

SoCLib, VCI_ANOC_Network

Tue, 20 Oct 2009 08:47:22 GMT

https://www.soclib.fr/trac/dev/wiki/Component/VciAnoc

ANOC stands for Asynchronous Network-on-Chip (NoC) and has been developed by the CEA-Leti. ANOC is a wormhole packet switching NoC. Its architecture is composed by five ports routers interconnected by bidirectional links using send/accept asynchronous handshake protocol. Thus, the ANOC protocol offers naturally a GALS architecture. As the ANOC routers are asynchronous, the entire end-to-end path traveling the packets is completely asynchronous.

The ANOC topology is not reduced to regular 2D mesh. Irregular 2D mesh or 2D torus topology can also be implemented as ANOC uses a source routing algorithm. Moreover, source routing can be used to minimize the congestion on some links, and thus reduce the packet latency. A flit is the smallest flow control unit of the network. Each flit contains two control bits, Begin of Packet (BOP) and End of Packet (EOP). BOP is set on the head flit, and EOP is set on the tail flit. Furthermore, the first flit of the packet contains the routing information and the router uses this “path-to-target” to decide the correct routing destination. The routing information is enclosed on 18-bits and two bits encodes each routing hop, which allows addressing a path of at most 9 router hops.

DDR Memory, Cache Memory

Sun, 14 Jun 2009 21:18:30 GMT

DDR Memory:

http://www.moikompas.ru/compas/ddr_memory

Cache memory:
http://www.moikompas.ru/compas/jacobs

Patent Watch

Sun, 14 Jun 2009 21:10:33 GMT

Patent Watch Issued on February:
http://www.moikompas.ru/compas/pw_feb

Patent Watch Issued on March:
http://www.moikompas.ru/compas/pw_march

Patent Watch Issued on September:
http://www.moikompas.ru/compas/pw_sep

The Most Important Patents in IC Design Industry:
http://www.moikompas.ru/compas/patents

Venture Funds Worldwide / Мировые Венчурные Фонды

Sat, 16 May 2009 08:54:56 GMT

http://www.moikompas.ru/compas/ventures

IC design people3

Fri, 13 Mar 2009 17:02:39 GMT

IC design people3:

http://www.moikompas.ru/compas/ic_people3

The ARM connected community

Fri, 06 Mar 2009 11:23:56 GMT

The ARM connected community:

http://www.moikompas.ru/compas/arm_community

Crypto-Processor Design Group

Sun, 22 Feb 2009 14:37:33 GMT

Crypto-Processor Design Group:
http://vsevteme.ru/network/249

OS Development (написание операционной системы)

Fri, 20 Feb 2009 20:39:23 GMT

OS Development (написание операционной системы):

http://www.moikompas.ru/compas/os_development

Fabless BackEnd Design

Fri, 20 Feb 2009 20:36:14 GMT

Fabless BackEnd Design:

http://www.moikompas.ru/compas/backend

IC design people

Tue, 27 Jan 2009 11:20:57 GMT

IC design people:

http://www.moikompas.ru/compas/ic_design_people

http://www.moikompas.ru/compas/ic_people2

Ru.Chip Company (Fabless)

Sun, 07 Dec 2008 00:45:23 GMT

http://moikompas.ru/compas/ruchip

"Google Inside" Group

Sun, 30 Nov 2008 04:34:13 GMT

"Google Inside" Group:

http://vsevteme.ru/network/248

Fabless IC Design Worldwide/ Мировой Fabless IC Design

Wed, 22 Oct 2008 02:15:09 GMT

Fabless IC Design Worldwide/ Мировой Fabless IC Design:

http://moikompas.ru/compas/fabless_worldwide

Energy Efficient Ethernet (EEE)

Sun, 05 Oct 2008 01:13:00 GMT

Тут новый стандарт хотят сделать в 2009 - Energy Efficient Ethernet (EEE)

http://www.scaleoutadvantage.techweb.com/news/fut_nwc20070528_ethernet.jhtml

Если сделать переходник с LACPDU на свой PDU (protocol data unit), то можно сильно оптимизировать распределение траффика из LAN в embedded

x86 Microprocessor Design Group

Fri, 19 Sep 2008 19:08:46 GMT

x86 Microprocessor Design Group:

http://vsevteme.ru/network/203

The Most Important Patents in IC Design Industry

Sat, 23 Aug 2008 19:50:11 GMT

The Most Important Patents in IC Design Industry:

http://moikompas.ru/compas/patents

SWARM - Software ARM

Sat, 23 Aug 2008 18:41:02 GMT

SWARM - Software ARM:
It is a modular simulation of an ARM 7 processor written in C++. It is cycle accurate, and models the datapath at the bus level. It is sufficiently complete that it will run microcontroller linux.

http://www.cl.cam.ac.uk/~mwd24/phd/swarm.html

Books on IC design

Sat, 23 Aug 2008 17:49:46 GMT

Books on IC design (essentials):

http://moikompas.ru/compas/ic_design_books

Open Pentium Architecture

Sat, 16 Aug 2008 00:09:50 GMT

Open Pentium Architecture:

www.openx86.com

VLIW Microprocessor Design

Wed, 13 Aug 2008 01:44:05 GMT

VLIW Microprocessor Design Group:

http://vsevteme.ru/network/188

OCP/STBus Plug-In Methodology

Wed, 06 Aug 2008 00:31:16 GMT

http://www.synopsys.com/sps/pdf/gspx_paper.pdf

Yahoo ASIC Design Group

Tue, 05 Aug 2008 20:59:51 GMT

Everything goes here, everything that is related to the ASIC world. No flames and no advertisements from agencies please. We discuss everything that appeals to the professionals in the ASIC field. Keywords: ASIC design, Verification,Vera, Specman, Synthesis, Verilog, VHDL, Synopsys, FPGA, CPLD, Altera, Xilinx, Atmel, DSP, EDA tools, job environment, place and route, PLI, Perl, Tcl, Nawk, Skill, Unix, C++, digital logic design, SOC, system design, CPU architecture, network, video, audio, DSP, chip architect.

http://tech.groups.yahoo.com/group/ASICDESIGN/#ans