Anton Gerasimov

Predator: A Predictable SDRAM Memory Controller

2009-12-20T15:58:25Z

http://www.es.ele.tue.nl/epicurus/publications/codes07.pdf

ARM Synchronization Primitives

2009-11-12T12:46:37Z

1.2.3. Memory barriers

To ensure a consistent memory view, it is architecturally defined that software must perform a Data Memory Barrier (DMB) operation:

between acquiring a resource, for example through locking a mutex or decrementing a semaphore, and making any access to that resource
before making a resource available, for example through unlocking a mutex or incrementing a semaphore

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGIEIE.html

Memory Management on the StrongARM

2009-11-11T11:35:51Z

Memory Management on the StrongARM SA-110: An Application Note

http://www.renan.org/ARM/doc/MMSAAN.pdf

Cell Broadband Engine processor DMA engines

2009-11-09T18:29:12Z

http://www.ibm.com/developerworks/power/library/pa-celldmas/
PPC/ SPE/ MFC Interface

SoCLib, VCI_ANOC_Network

2009-10-20T08:47:22Z

https://www.soclib.fr/trac/dev/wiki/Component/VciAnoc

ANOC stands for Asynchronous Network-on-Chip (NoC) and has been developed by the CEA-Leti. ANOC is a wormhole packet switching NoC. Its architecture is composed by five ports routers interconnected by bidirectional links using send/accept asynchronous handshake protocol. Thus, the ANOC protocol offers naturally a GALS architecture. As the ANOC routers are asynchronous, the entire end-to-end path traveling the packets is completely asynchronous.

The ANOC topology is not reduced to regular 2D mesh. Irregular 2D mesh or 2D torus topology can also be implemented as ANOC uses a source routing algorithm. Moreover, source routing can be used to minimize the congestion on some links, and thus reduce the packet latency. A flit is the smallest flow control unit of the network. Each flit contains two control bits, Begin of Packet (BOP) and End of Packet (EOP). BOP is set on the head flit, and EOP is set on the tail flit. Furthermore, the first flit of the packet contains the routing information and the router uses this “path-to-target” to decide the correct routing destination. The routing information is enclosed on 18-bits and two bits encodes each routing hop, which allows addressing a path of at most 9 router hops.

DDR Memory, Cache Memory

2009-06-14T21:18:30Z

DDR Memory:

http://www.moikompas.ru/compas/ddr_memory

Cache memory:
http://www.moikompas.ru/compas/jacobs

Patent Watch

2009-06-14T21:10:33Z

Patent Watch Issued on February:
http://www.moikompas.ru/compas/pw_feb

Patent Watch Issued on March:
http://www.moikompas.ru/compas/pw_march

Patent Watch Issued on September:
http://www.moikompas.ru/compas/pw_sep

The Most Important Patents in IC Design Industry:
http://www.moikompas.ru/compas/patents

Venture Funds Worldwide / Мировые Венчурные Фонды

2009-05-16T08:54:56Z

http://www.moikompas.ru/compas/ventures

IC design people3

2009-03-13T17:02:39Z

IC design people3:

http://www.moikompas.ru/compas/ic_people3

The ARM connected community

2009-03-06T11:23:56Z

The ARM connected community:

http://www.moikompas.ru/compas/arm_community

Crypto-Processor Design Group

2009-02-22T14:37:33Z

Crypto-Processor Design Group:
http://vsevteme.ru/network/249

OS Development (написание операционной системы)

2009-02-20T20:39:23Z

OS Development (написание операционной системы):

http://www.moikompas.ru/compas/os_development

Fabless BackEnd Design

2009-02-20T20:36:14Z

Fabless BackEnd Design:

http://www.moikompas.ru/compas/backend

IC design people

2009-01-27T11:20:57Z

IC design people:

http://www.moikompas.ru/compas/ic_design_people

http://www.moikompas.ru/compas/ic_people2

Ru.Chip Company (Fabless)

2008-12-07T00:45:23Z

http://moikompas.ru/compas/ruchip

"Google Inside" Group

2008-11-30T04:34:13Z

"Google Inside" Group:

http://vsevteme.ru/network/248

Fabless IC Design Worldwide/ Мировой Fabless IC Design

2008-10-22T02:15:09Z

Fabless IC Design Worldwide/ Мировой Fabless IC Design:

http://moikompas.ru/compas/fabless_worldwide

Energy Efficient Ethernet (EEE)

2008-10-05T01:13:00Z

Тут новый стандарт хотят сделать в 2009 - Energy Efficient Ethernet (EEE)

http://www.scaleoutadvantage.techweb.com/news/fut_nwc20070528_ethernet.jhtml

Если сделать переходник с LACPDU на свой PDU (protocol data unit), то можно сильно оптимизировать распределение траффика из LAN в embedded

x86 Microprocessor Design Group

2008-09-19T19:08:46Z

x86 Microprocessor Design Group:

http://vsevteme.ru/network/203

The Most Important Patents in IC Design Industry

2008-08-23T19:50:11Z

The Most Important Patents in IC Design Industry:

http://moikompas.ru/compas/patents

SWARM - Software ARM

2008-08-23T18:41:02Z

SWARM - Software ARM:
It is a modular simulation of an ARM 7 processor written in C++. It is cycle accurate, and models the datapath at the bus level. It is sufficiently complete that it will run microcontroller linux.

http://www.cl.cam.ac.uk/~mwd24/phd/swarm.html

Books on IC design

2008-08-23T17:49:46Z

Books on IC design (essentials):

http://moikompas.ru/compas/ic_design_books

Open Pentium Architecture

2008-08-16T00:09:50Z

Open Pentium Architecture:

www.openx86.com

VLIW Microprocessor Design

2008-08-13T01:44:05Z

VLIW Microprocessor Design Group:

http://vsevteme.ru/network/188

OCP/STBus Plug-In Methodology

2008-08-06T00:31:16Z

http://www.synopsys.com/sps/pdf/gspx_paper.pdf